L2 cache

In an Intel IA32 P4 processor, the size of each L2 cache line is32 bytes.

在Intel IA32P4处理器中，每条L2高速缓存线路的大小是32个字节。

This policy decides on whether a thread should be dispatch-stalled at the dispatch stage in the pipeline according to the detected or predicted L2 cache miss information.

该策略在流水线的派遣阶段实施停止派遣控制决策，根据检测到的或预测到的二级Cache失效信息决定是否停止派遣线程的指令到指令队列。

A Cooperative Replacement Algorithm for the L2 Cache of Cluster File Systems

一种集群文件系统二级缓存协同置换算法

The original Celeron design was a poor performer due to the lack of L2 cache.

原设计的赛扬是一个贫穷的演员，但由于缺乏二级缓存。

Through analyzing multi-core processors, we found that there are two key factors affecting its performance,: one is L2 cache hit rate of multi-core processor. the other is the utilization rate of multi-core processor line.

通过对多核处理器的分析，发现影响其性能的关键因素有两个：一个是多核处理器二级缓存的命中率另一个是多核处理器线路的利用率。

Multicore processor performances with different memory sharing levels are compared which help to determine to share the memory at the L2 cache level.

比较了不同共享级别条件下多核处理器的性能，确定了在二级Cache级别进行共享。

We perform experiments to validate the model and it shows that this model can accurately predict the L2 Cache misses.

利用实验验证了模型的有效性，结果表明该模型能够准确预测L2Cache的失效。

Then, we design and implement a Shared by Heterogeneity Processor L2 Cache sub-system to exploit the extra parallelism and locality in stream application, and improve the off-chip memory bandwidth. These lead to a more completed parallel hierarchy stream memory system.

针对流应用中各种可用的并行性和局域性，我们设计并实现了由异构处理器共享的二级缓存子系统，并对片外存储层次进行改进，完善了原有的存储层次结构。

Instead of the pixel filled mode under the low-resolution, index code resembled L2 Cache of PC was used.

同时，摒弃了低分辨率下常用的屏幕点阵填写模式，采用与PC机中高速二级缓存Cache命中技术相类似的索引码进行显示等。

Frequency predictor is used to record reused information of block not presented in L2 Cache.

频率预测器是用来记录L2Cache中没有出现的块的最近重用频率。

Experimental results show that the directory information was stored in the paper presented in the L2 Cache and directory-based cache coherence protocol improved, reducing the multi-core processors fetch latency, improves system performance.

实验结果证明，将目录信息存储在本文中提出的L2Cache中并对基于目录的Cache一致性协议改进后，减少了多核处理器的访存延迟，提升了系统性能。

However, the increasing number of processors cores on a single chip increases the demand on two critical resources: the shared L2 cache capacity and the off-chip pin bandwidth.

然而，在单芯片上集成越来越多的处理器内核增加了对两个关键资源的需求：共享二级缓存容量和片外引脚带宽。

The cache design support the global and "shared" management of the cooperative cache and support communication between L2 cache.

支持协同式Cache全局的、共享的管理方式以及二级Cache之间的数据传递。

A typical CMP ( Chip Multi-Processor) architecture often has a shared L2 cache and lower storage hierarchy. Sharing the L2 cache allows high cache utilization and avoids duplicating cache hardware resources.

在典型的多核处理器（CMP，Chip multi-Processor）体系结构中，多个处理器核共享二级高速缓存，这种方式不仅能够提高高速缓存的利用率，还能避免存储器硬件资源的浪费。

As a result, the overall performance of SMT processors is degraded. In this paper, we propose a novel fetch policy called MFP ( Multiple Fetch Priorities) to prevent the negative effects caused by L2 cache misses.

本文提出了一种基于多个取指优先级的同时多线程取指策略MFP（Multiple Fetch Priorities），用于减少L2cache失效给处理器性能带来的负面影响。

Discussion on L2 Cache storage infrastructure of broadcasting system

播出系统中二级缓存存储架构的探讨

Completed the design of the "Longtium D2" L2 cache, including the architecture design, hardware support, interconnection mechanism and the state machine of main controller etc.

完成了龙腾D2双核处理器中二级Cache的设计，包括整体结构的设计、硬件支持、互联机制、主控状态机的设计等。

To prefetch data streams from external memories, two prefetch buffers based on chain tables structure are constructed to predict and prefetch the data streams related with L2 cache missing.

本文采用两个基于链表结构的数据流预取缓冲器，识别并预取与二级Cache失效相关的数据流。

Full Custom Design and Realization of SRAM in L2 Cache Tag

二级Cache Tag中SRAM的全定制设计与实现

By using the EDMA channel linking mechanism of DSP, this system can transport video data from the FPGA unit to L2 cache of DSP without CPU interference, thus improving the performance and diminishing the system burden.

系统DSP部分巧妙利用EDMA传输链机制，在无需CPU干预的情况下，完成了视频数据从FPGA到L2的缓冲加载；

Based on a detailed analysis to the current prefetching coordination algorithm, the thesis found two problems: first, it has little effect for the random request, and cannot improve the utilization of L2 Cache significantly.

本文通过对当前的预取协调方法进行详细分析，发现其存在两个问题：第一，对于随机请求的影响较小，不能明显提高服务器端的利用率。